Most of the computer systems have power management tools incorporated within, that allow the system's processor to conserve power by entering power safe modes. Due to a variety of power safe modes it is essential that an operating system be able to intelligently determine which power safe mode to enter at a particular time. Some operating systems, especially those that support Advanced Configuration and Power Interface (ACPI), details of which may be found in Advanced Configuration and Power Interface Specification, Rev. 2.0 (Jul. 27, 2000), attempt to measure the duration of time that the Central Processing Unit (CPU) has been placed in power states, such as C1, C2, C3, etc. Depending on the duration of the low-power state the operating system may make an intelligent selection of a low-power state in the future. For example, if the CPU enters a C3 state and remains in the state only for a short time, the operating system may in the future decide to enter C2 state rather than C3 state. On the other hand, if the CPU enters C2 power state for a long time, the operating system may select a C3 state next time it needs to enter a low-power state.
In order to calculate the duration of a particular power state, the operating system needs to determine the time at which the CPU entered the low-power state and the time at which the CPU resumed execution of instructions.
For power states, such as C2 and C3, the processor initiates the transition to the state by accessing a register in a chipset, which halts the processor. Upon exiting the low-power state, the CPU starts the execution at an instruction next to the one that it completed executing prior to entering the low-power state. Thus, the operating system, is able to determine the entering and exiting time of the power state prior to resuming the execution of instructions.
However, the C1 power state is entered by the CPU executing a halt instruction, not by accessing a register. Exit from the C1 low-power state is interrupt driven and the CPU jumps directly to an interrupt service routine, which may be message based, pin based or any other type of interrupt routines. Thus, in a case of the C1 power state the operating system cannot directly measure the duration of time that the CPU was in the C1 power state because the first instruction that is executed does not result in the exit time being stored. The operating system can estimate the duration of the C1 power state, and in a case of an inaccurate estimation the selection of the next low-power state will reflect the inaccuracy.